`define MSBI 4    // Most significant Bit of DAC input

module vdsdac(
   clk50M,
   reset,
   iR, iG, iB,
   oR, oG, oB
);

input           clk50M;
input           reset;
input [`MSBI:0] iR, iG, iB;

output          oR, oG, oB;

wire clk270M;
vdac dacR( clk270M, reset, iR, oR );
vdac dacG( clk270M, reset, iG, oG );
vdac dacB( clk270M, reset, iB, oB );

wire clkout;
DCM DCM_INST2(.CLKFB(clkout), 
              .CLKIN(clk50M), 
              .DSSEN(GND1), 
              .PSCLK(GND1), 
              .PSEN(GND1), 
              .PSINCDEC(GND1), 
              .RST(reset),
              .CLKDV(), 
              .CLKFX(clk270M), 
              .CLKFX180(), 
              .CLK0(clkout),
              .CLK2X(), 
              .CLK2X180(), 
              .CLK90(), 
              .CLK180(), 
              .CLK270(), 
              .LOCKED(), 
              .PSDONE(), 
              .STATUS());
defparam DCM_INST2.CLK_FEEDBACK = "1X";
defparam DCM_INST2.CLKDV_DIVIDE = 2.0;
defparam DCM_INST2.CLKFX_DIVIDE = 5;
defparam DCM_INST2.CLKFX_MULTIPLY = 27;
defparam DCM_INST2.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_INST2.CLKIN_PERIOD = 20.000;
defparam DCM_INST2.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM_INST2.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam DCM_INST2.DFS_FREQUENCY_MODE = "HIGH";
defparam DCM_INST2.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_INST2.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_INST2.FACTORY_JF = 16'h8080;
defparam DCM_INST2.PHASE_SHIFT = 0;
defparam DCM_INST2.STARTUP_WAIT = "FALSE";

endmodule


module vdac(
    clk,
    reset,
    in,
    out
);

input  clk;
input  reset;
input [`MSBI:0] in;         // DAC input (excess 2**MSBI)

output out;                 // DAC output
reg    out;

reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [`MSBI+2:0] SigmaLatch; // Latches output of Sigma adder
reg [`MSBI+2:0] DeltaB;     // B input of Delta adder

always @(SigmaLatch)
   DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);

always @(in or DeltaB)              DeltaAdder = in + DeltaB;
always @(DeltaAdder or SigmaLatch)  SigmaAdder = DeltaAdder + SigmaLatch;

always @( posedge clk or posedge reset ) begin
   if ( reset ) begin
      SigmaLatch <= 1 << (`MSBI+1);
      out        <= 1'b0;
   end else begin
      SigmaLatch <= SigmaAdder;
      if ( in == 0 ) out <= 1'b0; else out <= SigmaLatch[`MSBI+2];
   end
end

endmodule